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ltc4300a-1/ltc4300a-2 1 4300a12fa typical application features description hot swappable 2-wire bus buffers the ltc ? 4300a series hot swappable 2-wire bus buffers allow i/o card insertion into a live backplane without corrup- tion of the data and clock busses. when the connection is made, the ltc4300a-1/ltc4300a-2 provide bidirectional buffering, keeping the backplane and card capacitances isolated. rise-time accelerator circuitry* allows the use of weaker dc pull-up currents while still meeting rise-time requirements. during insertion, the sda and scl lines are precharged to 1v to minimize bus disturbances. the ltc4300a-1 incorporates a cmos threshold digital enable input pin, which forces the part into a low current mode when driven to ground and sets normal operation when driven to v cc . it also includes an open drain ready output pin, which indicates that the backplane and card sides are connected together. the ltc4300a-2 replaces the enable pin with a dedicated supply voltage pin, v cc2 , for the card side, providing level shifting between 3.3v and 5v systems. both the backplane and card may be powered with supply voltages ranging from 2.7v to 5.5v, with no constraints on which supply voltage is higher. the ltc4300a-2 also replaces the ready pin with a digital cmos input pin, acc, which enables and disables the rise-time accelerator currents. the ltc4300a is available in a small 8-pin msop package. inputCoutput connection t plh applications n bidirectional buffer for sda and scl lines increases fanout n prevents sda and scl corruption during live board insertion and removal from backplane n isolates input sda and scl lines from output n compatible with i 2 c, i 2 c fast mode and smbus standards (up to 400khz operation) n low i cc chip disable: <1a (ltc4300a-1) n ready open drain output (ltc4300a-1) n 1v precharge on all sda and scl lines n supports clock stretching, arbitration and synchronization n 5v to 3.3v level translation (ltc4300a-2) n high impedance sda, scl pins for v cc = 0v n small msop 8-pin package n hot board insertion n servers n capacitance buffer/bus extender n desktop computer l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and hot swap and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. *protected by u.s. patents, including 6650174. r1 10k v cc 3.3v r2 10k enable sclin sclout sdain sdaout gnd ltc4300a-1 ready c1 0.01f 4300a12 ta01 r3 10k r4 10k output side 50pf input side 150pf 4300a12 ta02
ltc4300a-1/ltc4300a-2 2 4300a12fa electrical characteristics symbol parameter conditions min typ max units power supply v cc positive supply voltage l 2.7 5.5 v i cc supply current v cc = 5.5v, v sdain = v sclin = 0v, ltc4300a-1 l 5.1 7 ma i sd supply current in shutdown mode v enable = 0v, ltc4300a-1 0.1 a v cc2 card side supply voltage ltc4300a-2 l 2.7 5.5 v i vcc1 v cc supply current v sdain = v sclin = 0v, v cc1 = v cc2 = 5.5v, ltc4300a-2 3 4.1 ma i vcc2 v cc2 supply current v sdaout = v sclout = 0v, v cc1 = v cc2 = 5.5v, ltc4300a-2 2.1 2.9 ma start-up circuitry v pre precharge voltage sda, scl floating l 0.8 1.0 1.2 v t idle bus idle time l 50 95 150 s v en enable threshold voltage ltc4300a-1 0.5 ? v cc 0.9 ? v cc v v dis disable threshold voltage ltc4300a-1, enable pin 0.1 ? v cc 0.5 ? v cc v i en enable input current enable from 0v to v cc , ltc4300a-1 0.1 1 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, unless otherwise noted. pin configuration absolute maximum ratings v cc to gnd .................................................... C0.3 to 7v v cc2 to gnd (ltc4300a-2)............................ C0.3 to 7v sdain, sclin, sdaout, sclout .................. C0.3 to 7v ready, enable (ltc4300a-1) ...................... C0.3 to 7v acc (ltc4300a-2) ......................................... C0.3 to 7v operating temperature range ltc4300a-1c/ltc4300a-2c .................... 0c to 70c ltc4300a-1i/ltc4300a-2i .................. C40c to 85c storage temperature range .................. C65c to 125c lead temperature (soldering, 10 sec) ................... 300c (note 1) 1 2 3 4 enable/v cc2 * sclout sclin gnd 8 7 6 5 v cc sdaout sdain ready/acc* top view ms8 package 8-lead plastic msop *ltc4300a-2 t jmax = 125c, ja = 200c/w order information lead free finish tape and reel part marking package description temperature range ltc4300a-1cms8#pbf ltc4300a-1cms8#trpbf ltabf 8-lead plastic msop 0c to 70c ltc4300a-1ims8#pbf ltc4300a-1ims8#trpbf ltabg 8-lead plastic msop C40c to 85c ltc4300a-2cms8#pbf ltc4300a-2cms8#trpbf ltacf 8-lead plastic msop 0c to 70c ltc4300a-2ims8#pbf ltc4300a-2ims8#trpbf ltacg 8-lead plastic msop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc4300a-1/ltc4300a-2 3 4300a12fa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, unless otherwise noted. symbol parameter conditions min typ max units t phl enable delay, on-off ltc4300a-1 10 ns ready delay, off-on ltc4300a-1 10 ns t plh enable delay, off-on ltc4300a-1 95 s ready delay, on-off ltc4300a-1 10 ns i off ready off state leakage current ltc4300a-1 0.1 a v ol ready output low voltage i pullup = 3ma, ltc4300a-1 l 0.4 v rise-time accelerators i pullupac transient boosted pull-up current positive transition on sda,scl, v cc = 2.7v, slew rate = 1.25v/s (note 2), ltc4300a-2, acc = 0.7 ? v cc2 , v cc2 = 2.7v 12 ma v accdis accelerator disable threshold ltc4300a-2 0.3 ? v cc2 0.5 ? v cc2 v v accen accelerator enable threshold ltc4300a-2 0.5 ? v cc2 0.7 ? v cc2 v i vacc acc input current ltc4300a-2 0.1 1 a t pdoff acc delay, on/off ltc4300a-2 5 ns input-output connection v os input-output offset voltage 10k to v cc on sda, scl, v cc = 3.3v (note 3), ltc4300a-2, v cc2 = 3.3v, v in = 0.2v l 0 100 175 mv f scl, sda operating frequency guaranteed by design, not subject to test 0 400 khz c in digital input capacitance guaranteed by design, not subject to test 10 pf v ol output low voltage, input = 0v sda, scl pins, i sink = 3ma, v cc = 2.7v, v cc2 = 2.7v, ltc4300a-2 l 0 0.4 v i leak input leakage current sda, scl pins = v cc = 5.5v, ltc4300a-2, v cc2 = 5.5v 5 a timing characteristics f i2c i 2 c operating frequency (note 4) 0 400 khz t buf bus free time between stop and start condition (note 4) 1.3 s t hd,sta hold time after (repeated) start condition (note 4) 0.6 s t su,sta repeated start condition setup time (note 4) 0.6 s t su,sto stop condition setup time (note 4) 0.6 s t hd, dat data hold time (note 4) 300 ns t su, dat data setup time (note 4) 100 ns t low clock low period (note 4) 1.3 s t high clock high period (note 4) 0.6 s t f clock, data fall time (notes 4, 5) 20 + 0.1 ? c b 300 ns t r clock, data rise time (notes 4, 5) 20 + 0.1 ? c b 300 ns t phl,skew high-to-low propagation delay skew, scl-sda ltc4300a-1: v cc = 2.7v; v cc = 5.5v (note 6) l 0 75 ns ltc4300a-2: v cc = 2.7v, v cc2 = 5.5v; v cc = 5.5v; v cc2 = 2.7v (note 6) l 0 75 ns
ltc4300a-1/ltc4300a-2 4 4300a12fa C40 25 85 temperature (c) i cc (ma) 4300a12 g01 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 v cc = 5.5v v cc = 2.7v C50 C25 0 25 50 75 100 temperature (c) i pullupac (ma) 4300a12 g03 12 10 8 6 4 2 0 v cc = 2.7v v cc = 5v v cc = 3v typical performance characteristics electrical characteristics i pullupac vs temperature connection circuitry v out C v in i cc vs temperature (ltc4300a-1) input C output t phl vs temperature (ltc4300a-1) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: i pullupac varies with temperature and v cc voltage, as shown in the typical performance characteristics section. note 3: the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltage as a function of the pull-up resistor and v cc voltage is shown in the typical performance characteristics section. note 4: guaranteed by design, not subject to test. note 5: c b = total capacitance of one bus line in pf. note 6: these tests measure the difference in high-to-low propagation delay t phl between the clock and data channels. the delay on each channel is measured from the 50% point of the falling driven input signal to the 50% point of the output driven by the ltc4300a-1/ltc4300a-2. the skew is defined as (t phl(scl) C t phl(sda) ). testing is performed in both directionsfrom input bus to output bus and vice versa. tests are performed with approximately 500pf of distributed equivalent capacitance on each sda and scl pin. C50 C25 0 25 50 75 100 temperature (c) t phl (ns) 4300a12 g02 100 80 60 40 20 0 v cc = 2.7v v cc = 3.3v v cc = 5.5v c in = c out = 100pf r pullupin = r pullupout = 10k r pullup () 0 10,000 20,000 30,000 40,000 v out C v in (mv) 4300a12 g04 300 250 200 150 100 50 0 v cc = 3.3v v cc = 5v t a = 25c v in = 0v
ltc4300a-1/ltc4300a-2 5 4300a12fa pin functions enable/v cc2 (pin 1): chip enable pin/card supply volt- age. for the ltc4300a-1, this is a digital cmos threshold input pin. grounding this pin puts the part in a low current (<1a) mode. it also disables the rise-time accelerators, disables the bus precharge circuitry, drives ready low, isolates sdain from sdaout and isolates sclin from sclout. drive enable all the way to v cc for normal operation. connect enable to v cc if this feature is not being used. for the ltc4300a-2, this is the supply voltage for the devices on the card i 2 c busses. connect pull-up resistors from sdaout and sclout to this pin. place a bypass capacitor of at least 0.01f close to this pin for best results. sclout (pin 2): serial clock output. connect this pin to the scl bus on the card. sclin (pin 3): serial clock input. connect this pin to the scl bus on the backplane. gnd (pin 4): ground. connect this pin to a ground plane for best results. ready/acc (pin 5): connection flag/rise-time accelera- tor control. for the ltc4300a-1, this is an open-drain nmos output which pulls low when either enable is low or the start-up sequence described in the operation section has not been completed. ready goes high when enable is high and start-up is complete. connect a 10k resistor from this pin to v cc to provide the pull up. for the ltc4300a-2, this is a cmos threshold digital input pin that enables and disables the rise-time accelerators on all four sda and scl pins. drive acc all the way to the v cc2 supply voltage to enable all four accelerators; drive acc to ground to turn them off. sdain (pin 6): serial data input. connect this pin to the sda bus on the backplane. sdaout (pin 7): serial data output. connect this pin to the sda bus on the card. v cc (pin 8): main input power supply from backplane. this is the supply voltage for the devices on the back- plane i 2 c busses. connect pull-up resistors from sdain and sclin (and also from sdaout and sclout for the ltc4300a-1) to this pin. place a bypass capacitor of at least 0.01f close to this pin for best results.
ltc4300a-1/ltc4300a-2 6 4300a12fa block diagram 2-wire bus buffer and hot swap? controller (ltc4300a-1) 100k rch1 100k rch3 C + 5 C + 0.5pf ready 1 enable uvlo 3 sclin 4300a1 bd connect stop bit and bus idle 4 4 gnd connect 20pf rd s qb 0.5a 0.55v cc / 0.45v cc C + C + v cc C 1v 2ma 95s delay, rising only backplane-to-card connection connect connect 2 sclout 6 sdain backplane-to-card connection connect connect 7 sdaout 8v cc 1v precharge 100k rch2 100k rch4 slew rate detector 2ma slew rate detector 2ma slew rate detector 2ma slew rate detector connect enable
ltc4300a-1/ltc4300a-2 7 4300a12fa block diagram 2-wire bus buffer and hot swap controller (ltc4300a-2) 100k rch1 100k rch3 C + C + 0.5pf uvlo 3 sclin 4300a2 bd connect connect stop bit and bus idle 4 4 gnd 20pf rd s qb 0.5a 0.55v cc / 0.45v cc C + C + v cc2 C 1v 2ma backplane-to-card connection connect connect 2 sclout 6 sdain 8 v cc backplane-to-card connection connect connect 7 sdaout 1v cc2 5 acc 1v precharge 100k rch2 100k rch4 connect slew rate detector 2ma slew rate detector 2ma slew rate detector acc acc 2ma slew rate detector 95s delay, rising only
ltc4300a-1/ltc4300a-2 8 4300a12fa operation another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. input to output offset voltage when a logic low voltage, v low1 , is driven on any of the ltc4300as data or clock pins, the ltc4300a regulates the voltage on the other side of the chip (call it v low2 ) to a slightly higher voltage, as directed by the following equation: v low2 = v low1 + 75mv + (v cc /r) ? 100 where r is the bus pull-up resistance in ohms. for ex- ample, if a device is forcing sdaout to 10mv where v cc = 3.3v and the pull-up resistor r on sdain is 10k, then the voltage on sdain = 10mv + 75mv + (3.3/10000) ? 100 = 118mv. see the typical performance character- istics section for curves showing the offset voltage as a function of v cc and r. propagation delays during a rising edge, the rise-time on each side is deter- mined by the combined pull-up current of the ltc4300a boost current and the bus resistor and the equivalent capacitance on the line. if the pull-up currents are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. this effect is displayed in figure 1 for v cc = 3.3v and a 10k pull-up resistor on each side (50pf on one side and 150pf on the other). since the output side has less capacitance than the input, it rises faster and the effective t plh is negative. there is a finite propagation delay, t phl , through the con- nection circuitry for falling waveforms. figure 2 shows the falling edge waveforms for the same v cc , pull-up resistors and equivalent capacitance conditions as used in figure 1. an external nmos device pulls down the volt- age on the side with 150pf capacitance; the ltc4300a pulls down the voltage on the opposite side, with a delay of 55ns. this delay is always positive and is a function of start-up when the ltc4300a first receives power on its v cc pin, either during power-up or during live insertion, it starts in an undervoltage lockout (uvlo) state, ignoring any activity on the sda and scl pins until v cc rises above 2.5v. for the ltc4300a-2, the part also waits for v cc2 to rise above 2v. this ensures that the part does not try to function until it has enough voltage to do so. during this time, the 1v precharge circuitry is also ac- tive and forces 1v through 100k nominal resistors to the sda and scl pins. because the i/o card is being plugged into a live backplane, the voltage on the backplane sda and scl busses may be anywhere between 0v and v cc . precharging the scl and sda pins to 1v minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the i/o card. once the ltc4300a comes out of uvlo, it assumes that sdain and sclin have been inserted into a live system and that sdaout and sclout are being powered up at the same time as itself. therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. when either one occurs, the part also verifies that both the sdaout and sclout voltages are high. when all of these conditions are met, the input-to-output connection circuitry is activated, joining the sda and scl busses on the i/o card with those on the backplane, and the rise time accelerators are enabled. connection circuitry once the connection circuitry is activated, the functionality of the sdain and sdaout pins is identical. a low forced on either pin at any time results in both pin voltages being low. for proper operation, logic low input voltages should be no higher than 0.4v with respect to the ground pin voltage of the ltc4300a. sdain and sdaout enter a logic high state only when all devices on both sdain and sdaout release high. the same is true for sclin and sclout. this important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the ltc4300a.
ltc4300a-1/ltc4300a-2 9 4300a12fa operation supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. the typical performance characteristics section shows t phl as a function of temperature and voltage for 10k pull-up resistors and 100pf equivalent capacitance on both sides of the part. by comparison with figure 2, the v cc = 3.3v curve shows that increasing the capacitance from 50pf to 100pf results in a t phl increase from 55ns to 75ns. larger output capacitances translate to longer delays (up to 150ns). users must quantify the difference in propaga- tion times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. rise-time accelerators once connection has been established, rise-time accelera- tor circuits on all four sda and scl pins are activated. these allow the user to choose weaker dc pull-up cur- rents on the bus, reducing power consumption while still meeting system rise-time requirements. during positive bus transitions, the ltc4300a switches in 2ma (typical) of current to quickly slew the sda and scl lines once their dc voltages exceed 0.6v. using a general rule of 20pf of capacitance for every device on the bus (10pf for the device and 10pf for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 1.25v/s to guarantee activation of the accelerators. for example, assume an smbus system with v cc = 3v, a 10k pull-up resistor and equivalent bus capacitance of 200pf. the rise-time of an smbus system is calculated from (v il(max) C 0.15v) to (v ih(min) + 0.15v), or 0.65v to 2.25v. it takes an rc circuit 0.92 time constants to traverse this voltage for a 3v supply; in this case, 0.92 ? (10k ? 200pf) = 1.84s. thus, the system exceeds the maximum allowed rise-time of 1s by 84%. however, using the rise-time accelerators, which are activated at a dc threshold of below 0.65v, the worst-case rise-time is: (2.25v C 0.65v) ? 200pf/1ma = 320ns, which meets the 1s rise-time requirement. ready digital output (ltc4300a-1) this pin provides a digital flag which is low when either enable is low or the start-up sequence described earlier in this section has not been completed. ready goes high when enable is high and start-up is complete. the pin is driven by an open drain pull-down capable of sinking 3ma while holding 0.4v on the pin. connect a resistor of 10k to v cc to provide the pull-up. this feature is available for the ltc4300a-1 only. enable low current disable (ltc4300a-1) grounding the enable pin disconnects the backplane side from the card side, disables the rise-time accelerators, drives ready low, disables the bus precharge circuitry and puts the part in a near-zero current state. when the pin voltage is driven all the way to v cc , the part waits for data transactions on both the backplane and card sides to be complete (as described in the start-up section) before reconnecting the two sides. this feature is available for the ltc4300a-1 only. acc boost current enable (ltc4300a-2) users having lightly loaded systems may wish to disable the rise-time accelerators. driving this pin to ground turns off the rise-time accelerators on all four sda and scl pins. driving this pin to the v cc2 voltage enables normal operation of the rise-time accelerators, as described in the rise-time accelerators section above. this feature is available for the ltc4300a-2 only. figure 1. inputCoutput connection t plh figure 2. inputCoutput connection t phl output side 50pf input side 150pf 4300a12 f01 input side 150pf output side 50pf 4300a12 f02
ltc4300a-1/ltc4300a-2 10 4300a12fa applications information resistor pull-up value selection the system pull-up resistors must be strong enough to provide a positive slew rate of 1.25v/s on the sda and scl pins, in order to activate the boost pull-up currents during rising edges. choose maximum resistor value r using the formula: r (v cc(min) C 0.6) (800,000) / c where r is the pull-up resistor value in ohms, v cc(min) is the minimum v cc voltage and c is the equivalent bus capacitance in picofarads (pf). in addition, regardless of the bus capacitance, always choose r 16k for v cc = 5.5v maximum, r 24k for v cc ? =? 3.6v maximum. the start-up circuitry requires logic high voltages on sdaout and sclout to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. live insertion and capacitance buffering application figures 3 through 6 illustrate the usage of the ltc4300a in applications that take advantage of both its hot swap controlling and capacitance buffering features. in all of figure 3. inserting multiple i/o cards into a live backplane using the ltc4300a-1 in a compactpci system staggered connector r13 10k r12 10k r14 10k i/o peripheral card n enable sdain sclin u3 ltc4300a-1 v cc gnd cardn_scl cardn_sda sdaout sclout ready enable sdain sclin v cc gnd sdaout sclout ready enable card enable/disable sdain sclin v cc gnd sdaout sclout ready 4300a12 f03 ttt r9 10k r8 10k r10 10k i/o peripheral card 2 u2 ltc4300a-1 card2_scl card2_sda staggered connector staggered connector r5 10k r4 10k r6 10k i/o peripheral card 1 u1 ltc4300a-1 card_scl card_sda r1 10k v cc r2 10k backplane backplane connector sda bd_sel scl c1 0.01f r3 10k r7 10k r11 10k c3 0.01f c5 0.01f power supply hot swap power supply hot swap power supply hot swap card enable/disable card enable/disable
ltc4300a-1/ltc4300a-2 11 4300a12fa applications information these applications, note that if the i/o cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. placing a ltc4300a on the edge of each card, however, isolates the card capacitance from the backplane. for a given i/o card, the ltc4300a drives the capacitance of everything on the card and the backplane must drive only the capacitance of the ltc4300a, which is less than 10pf. figure 3 shows the ltc4300a-1 in a compactpci configu- ration. connect v cc and enable to the output of one of the compactpci power supply hot swap circuits. use a pull-up resistor to enable for a card side enable/disable. v cc is monitored by a filtered uvlo circuit. with the v cc voltage powering up after all other pins have established connection, the uvlo circuit ensures that the backplane and card data and clock busses are not connected until the transients associated with live insertion have settled. owing to their small capacitance, the sdain and sclin pins cause minimal disturbance on the backplane busses when they make contact with the connector. figure 4 shows the ltc4300a-2 in a compactpci con- figuration. the ltc4300a-2 receives its v cc voltage from one of the long early power pins. because this power is not switched, add a 5 to 10 resistor between the v cc pins of the connector and the ltc4300a-2, as shown in figure 4. inserting multiple i/o cards into a live backplane using the ltc4300a-2 in a compactpci system c1 0.01f c3 0.01f c5 0.01f r13 10k r12 10k r14 10k i/o peripheral card n v cc sdain sclin u3 ltc4300a-2 v cc2 gnd cardn_scl cardn_sda sdaout sclout acc v cc sdain sclin v cc2 gnd sdaout sclout acc v cc sdain sclin v cc2 gnd sdaout sclout acc 4300a12 f04 ttt r9 10k r8 10k r10 10k i/o peripheral card 2 u2 ltc4300a-2 card2_scl card2_sda r5 10k r4 10k r6 10k i/o peripheral card 1 u1 ltc4300a-2 c2 0.01f 5.1 card_scl card_sda v cc2 backplane backplane connector sda scl v cc bd_sel staggered connector staggered connector staggered connector power supply hot swap c4 0.01f 5.1 power supply hot swap c6 0.01f 5.1 power supply hot swap r1 10k r2 10k
ltc4300a-1/ltc4300a-2 12 4300a12fa the figure. in addition, make sure that the v cc bypassing on the backplane is large compared to the 0.01f bypass capacitor on the card. establishing early power v cc ensures that the 1v precharge voltage is present at the sdain and sclin pins before they make contact. con- nect v cc2 to the output of one of the compactpci power supply hot swap circuits. v cc2 is monitored by a filtered uvlo circuit. with the v cc2 voltage powering up after all other pins have established connection, the uvlo circuit ensures that the backplane and card data and clock busses are not connected until the transients associated with live insertion have settled. figure 5 shows the ltc4300a-1 in a pci application, where all of the pins have the same length. in this case, connect an rc series circuit on the i/o card between v cc and enable. an rc product of 10ms provides a filter to prevent the ltc4300a-1 from becoming activated until the transients associated with live insertion have settled. figure 5. inserting multiple i/o cards into a live backplane using the ltc4300a-1 in a pci system figure 6 shows the ltc4300a-2 in an application where the user has a custom connector with pins of three different lengths available. making v cc2 the shortest pin ensures that all other pins are firmly connected before v cc2 receives any voltage. a filtered uvlo circuit on v cc2 ensures that the v cc2 pin is firmly connected before the ltc4300a-2 connects the backplane to the card. repeater/bus extender application users who wish to connect two 2-wire systems separated by a distance can do so by connecting two ltc4300a-1s back-to-back, as shown in figure 7. the i 2 c specification allows for 400pf maximum bus capacitance, severely limiting the length of the bus. the smbus specification places no restriction on bus capacitance, but the limited impedances of devices connected to the bus require systems to remain small if rise- and fall-time specifica- tions are to be met. the strong pull-up and pull-down impedances of the ltc4300a-1 are capable of meeting r3 100k enable sdain sclin v cc gnd sdaout sclout ready enable sdain sclin v cc gnd sdaout sclout ready 4300a12 f05 r9 10k r8 10k r10 10k i/o peripheral card 2 u2 ltc4300a-1 card2_scl card2_sda r5 10k r4 10k i/o peripheral card 1 u1 ltc4300a-1 c2 0.1f r7 100k c4 0.1f card_scl card_sda r1 10k v cc r2 10k backplane backplane connector sda scl c1 0.01f c3 0.01f r6 10k t t t applications information
ltc4300a-1/ltc4300a-2 13 4300a12fa figure 6. inserting multiple i/o cards into a live backplane using the ltc4300a-2 with a custom connector figure 7. repeater/bus extender application staggered connector v cc sdain sclin v cc2 gnd sdaout sclout acc v cc sdain sclin v cc2 gnd sdaout sclout acc 4300a12 f06 r9 10k r8 10k i/o peripheral card 2 u2 ltc4300a-2 card2_scl card2_sda staggered connector r5 10k r4 10k i/o peripheral card 1 u1 ltc4300a-2 c2 0.01f c4 0.01f card_scl card_sda r1 10k r2 10k v cc2 backplane backplane connector sda scl v cc c1 0.01f c3 0.01f r10 10k r6 10k t t t r1 10k r3 5.1k r5 10k r2 5.1k v cc = 5v r4 10k r7 10k r8 10k 2-wire system 1 enable sdain sclin ltc4300a-1 gnd v cc c1 0.01f sdaout sclout ready scl1 to other system 1 devices sda1 c2 0.01f r6 10k 2-wire system 2 ltc4300a-1 enable sdain sclin 4300a12 f07 sdaout sclout ready long distance bus v cc scl1 sda1 to other system 2 devices gnd v cc applications information
ltc4300a-1/ltc4300a-2 14 4300a12fa applications information rise- and fall-time specifications for 1nf of capacitance, thus allowing much more interconnect distance. in this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed v ol specification with respect to the ground at the other end. in addition, the connection circuitry offset voltages of the back-to- back ltc4300a-1s add together, directly contributing to the same problem. systems with disparate supply voltages (ltc4300a-1) in large 2-wire systems, the v cc voltages seen by devices at various points in the system can differ by a few hun- dred millivolts or more. this situation is well modelled by a series resistor in the v cc line, as shown in figure 8. for proper operation of the ltc4300a-1, make sure that v cc(bus) v cc(ltc4300a) C 0.5v. 5v to 3.3v level translator and power supply redundancy (ltc4300a-2) systems requiring different supply voltages for the back- plane side and the card side can use the ltc4300a-2, as shown in figure 9. the pull-up resistors on the card side connect from sdaout to sclout to v cc2 , and those on the backplane side connect from sdain and sclin to v cc . the ltc4300a-2 functions for voltages ranging from 2.7v to 5.5v on both v cc and v cc2 . there is no constraint on the voltage magnitudes of v cc and v cc2 with respect to each other. this application also provides power supply redundancy. if the v cc2 voltage falls below its uvlo threshold, the ltc4300a-2 disconnects the backplane from the card, so that the backplane can continue to function. if the v cc voltage falls below its uvlo threshold and the v cc2 volt- age remains active, ground the acc pin to ensure proper operation. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 C 6 typ detail a detail a gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f)
ltc4300a-1/ltc4300a-2 15 4300a12fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 7/12 added t phl,skew parameter to electrical characteristics 3
ltc4300a-1/ltc4300a-2 16 4300a12fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2001 lt 0712 rev a ? printed in usa related parts typical applications part number description comments ltc1380/ltc1393 single-ended 8-channel/differential 4-channel analog mux with smbus interface low r on : 35 single-ended/70 differential, expandable to 32 single or 16 differential channels ltc1427-50 micropower, 10-bit current output dac with smbus interface precision 50a 2.5% tolerance over temperature, 4 selectable smbus addresses, dac powers up at zero or mid-scale ltc1623 dual high side switch controller with smbus interface 8 selectable addresses/16-channel capability ltc1663 smbus interface 10-bit rail-to-rail micropower dac dnl < 0.75lsb max, 5-lead sot-23 package ltc1694/ltc1694-1 smbus accelerator improved smbus/i 2 c rise-time, ensures data integrity with multiple smbus/i 2 c devices lt1786f smbus controlled ccfl switching regulator 1.25a, 200khz, floating or grounded lamp configurations ltc1695 smbus/i 2 c fan speed controller in thinsot? 0.75 pmos 180ma regulator, 6-bit dac ltc1840 dual i 2 c fan speed controller two 100a 8-bit dacs, two tach inputs, four gpi0 figure 8. system with disparate v cc voltages figure 9. 5v to 3.3v level translator r1 10k v cc (bus) r2 10k r drop v cc (ltc4300a) sda scl 4300a12 f08 r4 10k r5 10k r3 10k sdain enable sclin u1 ltc4300a-1 v cc gnd scl2 sda2 sdaout sclout ready c2 0.01f v cc2 gnd sdaout sclout sdain sclin acc v cc r2 10k r3 10k card_v cc , 3.3v card_scl card_sda c2 0.01f c1 0.01f r1 10k v cc 5v r4 10k u1 ltc4300a-2 scl sda 4300a12 f09

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